Semiconductor package

ABSTRACT

Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.

REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation for U.S. application Ser. No. 15/966,382, filed on Apr. 30, 2018, which is a Continuation of U.S. application Ser. No. 15/219,593, filed on Jul. 26, 2016 (now U.S. Pat. No. 9,960,125, issued on May 1, 2018), which is a Continuation of U.S. application Ser. No. 14/503,932, filed on Oct. 1, 2014 (now U.S. Pat. No. 9,431,367 issued on Aug. 30, 2016), which is a Divisional of U.S. application Ser. No. 13/597,868, filed on Aug. 29, 2012 (now U.S. Pat. No. 8,872,326 issued on Oct. 28, 2014). The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety.

BACKGROUND

With the continued evolution of semiconductor technologies, semiconductor chips/dies are becoming increasingly smaller. In the meantime, more functions are being integrated into the semiconductor dies. Accordingly, the semiconductor dies have increasingly greater numbers of input/output (I/O) pads packed into smaller areas. As a result, the packaging of the semiconductor dies becomes more important and more challenging.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a cross-sectional view of a package, in accordance with some embodiments.

FIG. 1B is a cross-sectional view of a portion of a package, in accordance with some embodiments.

FIG. 1C is a cross-section view of two dies bonded to an interconnecting structure, in accordance with some embodiments.

FIGS. 2A-2G are cross-sectional views of a sequential process flow of forming an interconnecting structure, in accordance with some embodiments.

FIGS. 3A-3H are cross-sectional views of a sequential process flow of forming a package, in accordance with some embodiments.

DETAILED DESCRIPTION

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.

FIG. 1A is a cross-sectional view of a package 100, in accordance with some embodiments. Package 100 includes a package structure 110 and a die 120. Package structure 110 includes semiconductor dies 111 and 112. In some embodiments, each of the semiconductor dies 111 and 112 includes a semiconductor substrate as employed in a semiconductor integrated circuit fabrication, and integrated circuits may be formed therein and/or thereupon. The semiconductor substrate refers to any construction comprising semiconductor materials, including, but not limited to, bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements may also be used. The semiconductor substrate may further comprise a plurality of isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may define and isolate the various microelectronic elements. Examples of the various microelectronic elements that may be formed in the semiconductor substrate include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.); resistors; diodes; capacitors; inductors; fuses; and other suitable elements. Various processes are performed to form the various microelectronic elements including deposition, etching, implantation, photolithography, annealing, and/or other suitable processes. The microelectronic elements are interconnected to form the integrated circuit device, such as a logic device, memory device (e.g., SRAM), RF device, input/output (I/O) device, system-on-chip (SoC) device, combinations thereof, and other suitable types of devices.

Semiconductor dies 111 and 112 are disposed on a substrate 115, which has contacts 116 on a surface thereof. Substrate 115 of package structure 110 has interconnect structures 117 connecting contacts 116 on one surface of substrate 115 to contacts 118 on an opposing surface of the substrate, as shown in FIG. 1A. Semiconductor dies 111 and 112 are electrically connected to contacts 116 by wires 113 and 114 respectively, in accordance with some embodiments. Semiconductor dies 111 and 112 may also be connected to contacts 116 by other means. Interconnect structures 117 in substrate 115 may include metal lines and vias. In some embodiments, the vias of interconnect structures 117 include through substrate vias (TSVs), or through substrate holes (TSHs). Contacts 118 on the opposing surface of substrate 115 include metal pads. Contacts 118 may also include a solder layer (not shown) prior to bonding with an interconnecting structure 130. The solder layer forms a portion of each connector 119. Connectors 119, such as solder bumps or solder balls, are attached to contacts 118. In some embodiments, the widths (or diameters) of connectors 119 are in a range from about 100 μm to about 400 μm. Connectors 119 and contacts 118 form bonding structures 124.

As described above, package 100 also includes die 120. Die 120 has contacts 122, which are surrounded by one or more passivation layers (not shown). In some embodiments, contacts 122 include metal pads 123 and bumps formed over metal pads 123. The bumps of contacts 122 may be solder bumps and/or may include copper pillars. The solder bumps of contacts 122 form bonding structures 125 between dies 120 and interconnecting structure 130. In some embodiments, the widths (or diameters) of bonding structure 125 are in a range from about 20 μm to about 100 μm. Connectors 119 are larger than contacts 122, in accordance with some embodiments.

A distance between a bottom surface of package structure 110 to a top surface of interconnecting structure 130 is labeled as H₁ in FIG. 1A. In some embodiments, H₁ is in a range from about 100 μm to about 400 μm. FIG. 1A also shows the thickness of die 120 is H₂. H₂ is smaller than H₁, which allows die 120 to utilize a space between package structure 110 and interconnecting structure 130.

As shown in FIG. 1A, package structure 110 and die 120 are disposed over and electrically connected to interconnecting structure 130. The interconnecting structure 130 includes one or more dielectric layers, such as dielectric layers 131 and 132. The dielectric layers 131 and 132 may be soft (or yielding) to absorb stress of the bonding process(es) involved in forming package 100. The material for each of dielectric layers 131 and 132 may be selected from photo-definable solder resists, a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), molding compound, and the like.

The interconnecting structure 130 has small contacts 133 bonding with contacts 122 on die 120 to form bonded structures 125. The interconnecting structure 130 also has large contacts 134 bonding with connectors 119 of package structure 110 to form bonded structures 124. Small contacts 133 are smaller than large contacts 134, in accordance with some embodiments. Further, interconnecting structure 130 has contacts 135 bonding with connecting elements 140, which are used to make external connections with an external substrate, such as a printed circuit board (PCB), or another package. A height of connecting element 140 is labeled as H₅ in FIG. 1A. In some embodiments, H₅ is in a range from about 100 μm to about 400 μm.

In some embodiments, dielectric layer 131 has a thickness in a range from about 3 μm to about 25 μm. In some embodiments, passivation layer 132 has a thickness in a range from about 3 μm to about 15 μm. A total thickness of interconnecting structure 130 is labeled as H₃ in FIG. 1A. In some embodiments, H₃ is in a range from about 6 μm to about 30 μm. In some embodiments, H₃ is equal to or less than about 30 μm. In some embodiments, H₃ is equal to or less than about 25 μm.

In the embodiment of FIG. 1A, contacts 135 are connected to metal lines 136, which provide electrical connections between bonded structures 125, 124, and 126. Metal lines 136 functions as a redistribution layer (RDL) and enables fan-out connection of die 120, which allows electrical connections beyond the edges (or boundaries) of die 120. The embodiment of FIG. 1A includes only one metal layer. However, a RDL (or RDLs) could include multiple metal layers, which could be interconnected by vias. In some embodiments, contacts 133 and 134 include an under bump metallurgy (UBM) layer 211, which may acts as a diffusion barrier layer between contacts 133, 134 with contacts 135 and a plating-enabling layer. Additional detailed description is provided below.

In some embodiments, widths of contacts 133 are in a range from about 20 μm to about 100 μm. In some embodiments, widths of contacts 134 are in a range from about 100 μm to about 400 μm. In the embodiment of FIG. 1A, contacts 135 include a conductive layer 208 and a barrier layer 205. Additional detailed description of these layers and formation method(s) is provided below.

In the embodiment of FIG. 1A, package structure 110 is covered by a molding layer (or a molding compound) 145. In some embodiments, the molding layer 145 includes epoxy, silicon, silica filler, and/or other types of polymers. In the embodiment of FIG. 1A, molding layer 145 also fills a space between package structure 110 and interconnecting structure 130. In some embodiments, molding layer 145 also acts as an underfill (UF) and fills a space between die 120 and interconnecting structure 130. Under such circumstance, the molding layer 145 is an underfill molding (MUF) compound and is applied on a surface of interconnecting structure 130 after both die 120 and package structure 110 are bonded to interconnecting structure 130. In some embodiments, an underfill 144 is applied after die 120 is bonded to interconnecting structure 130, as shown in FIG. 1B in accordance with some embodiments. After underfill 144 is applied, package structure 110 is then placed over and bonded to interconnecting structure 130. A thickness of package structure 110 above interconnecting structure 130 is labeled as H₄ in FIG. 1A. In some embodiments, H₄ is in a range from about 350 μm to 1000 μm. A total thickness of package 110 and interconnecting structure 130 is labeled as H₆ in FIG. 1A. In some embodiments, H₆ is in a range from about 350 μm to 1050 μm. H₆ is lower than other packaging structures, such as in a range from about 1000 μm to about 1500 μm. Therefore, package 100 has low z-axial form factor (or total thickness of package 100).

In the embodiment of FIG. 1A, die 120 and package structure 110 are bonded to interconnecting structure 130. In some embodiments, there are more than one die underneath package structure 110. In the embodiment of FIG. 1C, two dies 120′ and 120″ are bonded to an interconnecting structure 130′, in accordance with some embodiments. In the embodiment of FIG. 1C, a package structure 110′ is placed over dies 120′ and 120″.

FIGS. 2A-2G are cross-sectional views of a sequential process flow of forming interconnecting structure 130, in accordance with some embodiments. In FIG. 2A, an adhesive layer 202 is formed on a carrier 201. Carrier 201 is made of glass, in accordance with some embodiments. However, other materials may also be used for carrier 201. Adhesive layer 202 is disposed, for example, laminated, on carrier 201. Adhesive layer 202 may be formed of a glue, or may be a lamination layer formed of a foil. After the adhesion layer 202 is formed, a passivation layer 203 is formed and patterned to form contact openings 204 on adhesion layer 202, as shown in FIG. 2B in accordance with some embodiments. In some embodiments, the passivation layer 203 is a dielectric material. In some embodiments, the passivation layer 203 is a polymer. In some embodiments, passivation layer 203 is a photo-sensitive polymer and can be patterned without a photoresist layer.

After contact openings 204 are formed, a barrier layer 205 is formed to cover exposed surfaces of passivation layer 203 on carrier 201, as shown in FIG. 2C in accordance with some embodiments. The barrier layer 205 is a conductive layer and prevents the diffusion of copper deposited to fill openings 204. In some embodiments, the barrier layer 205 is made of Ti. In some embodiments, a copper seed layer (not shown) is formed over the barrier layer 205. In some embodiments, the barrier layer 205 and/or the copper seed layer are deposited by physical vapor deposition (PVD). After the barrier layer 205 is formed, a photoresist layer 206 is then formed over the barrier layer. In FIG. 2C, a photoresist layer 206 is formed over barrier layer 205. The photoresist layer 206 is formed by a spin-on process (wet process) in some embodiments. In some other embodiments, the photoresist layer 206 is a dry photoresist layer, which is adhered to the surface of barrier layer 205, which may be covered by a copper seed layer (not shown). The photoresist layer 206 is then patterned to define openings 207 for forming interconnection, as shown in FIG. 2C.

In FIG. 2D, a conductive layer 208 is formed in openings 207 and 204, in accordance with some embodiments. The conductive layer 208 is made of copper or a copper alloy in some embodiments. Conductive layer 208 includes metal(s) such as aluminum, nickel, gold, silver, platinum, alloy of the above-mentioned metals, or combinations thereof, in accordance with some embodiments. In some embodiments, the conductive layer 208 is formed by plating. Excess conductive layer 208, or regions of conductive layer 208 that are too thick, is removed by a removal process, such as chemical-mechanical polishing (CMP), in accordance with some embodiments. The photoresist layer 206 is then removed. For example, if photoresist layer 206 is a dry photoresist film, it can be removed by peeling. In some embodiments, the photoresist layer 206 is removed by an etching process. Portions of barrier layer 205 covered by the photoresist layer 206 is exposed after the photoresist layer 206 is removed. The exposed portions of barrier layer 205 is then removed as shown in FIG. 2D. In some embodiments, the exposed portions of barrier layer 205 are removed by an etching process.

In FIG. 2E, another passivation layer 209 is deposited and patterned over passivation layer 203 and conductive layer 208, in accordance with some embodiments. In some embodiments, the passivation layer 209 is a dielectric material. In some embodiment, the passivation layer 209 is a polymer. In some embodiments, passivation layer 209 is a photo-sensitive polymer and can be patterned without a photoresist layer. The patterning process forms openings 210. After openings 210 are formed, an under bump metallurgy (UBM) layer 211 is deposited on surfaces of passivation layer 209, in accordance with some embodiments. In some embodiments, the UBM layer 211 includes a diffusion barrier layer and a seed layer. The diffusion barrier layer may also function as an adhesion layer (or a glue layer), in some embodiments. The diffusion barrier layer may be made of Ta, TaN, Ti, TiN, or combinations thereof. The seed layer is made of a material for enabling later deposition of a conductive layer. In some embodiments, the UBM layer 211 includes a diffusion barrier layer formed of Ti and a seed layer formed of Cu. In some embodiments, both the diffusion barrier layer, such as a Ti layer, and the seed layer, such as a Cu layer, are deposited by physical vapor deposition (PVD) (or sputtering) methods.

After UBM layer 211 is formed, a photoresist layer 212 is formed over the UBM layer, as shown in FIG. 2F in accordance with some embodiments. The photoresist layer 212 may be a dry or a wet photoresist. Photoresist layer 212 is patterned to define openings 213 that substantially align with openings 210. After the patterning process is completed, a conductive layer 214 is formed to fill openings 210 and 213. In some embodiments, the conductive layer 214 includes copper, aluminum, copper alloy, or other mobile conductive materials. In some embodiments, the conductive layer 214 is made of solder.

In some embodiments, the conductive layer 214 includes two sub-layers. One sub-layer is a metal layer, which is made of copper, aluminum, copper alloy, or other conductive materials with low resistivity. Another sub-layer that covers the previously-mentioned sub-layer is made of solder. In some embodiments, a protective layer 215 is formed to cover the conductive layer 214, as shown in FIG. 2G, in accordance to some embodiments. Protective layer 215 is optional in some embodiments. Afterwards, the photoresist layer 212 is removed and UBM layer 211 exposed by the removal of the photoresist layer is also removed. In some embodiments, the conductive layer 214 is deposited by plating. The protective layer 215 protects a surface of the conductive layer 214 from oxidation. In some embodiments, the protective layer is made of Ni, or one of organic surface protection (OSP) materials. In some embodiments, the UBM layer 211, the conductive layer 214, and the optional protective layer 215 form contacts 133 and 134. The contacts shown in FIG. 2G are contacts 133 or 134.

The UBM layer 211 and the conductive layer 214 form bump structures, in accordance with some embodiments. In some embodiments, the bump structures are copper posts. Exemplary details of materials, structures, and forming methods of forming copper posts are described in U.S. patent application Ser. No. 12/846,353, titled “Mechanisms for Forming Copper Pillar Bumps” and filed on Jul. 29, 2010, which is incorporated herein in its entirety. The structure formed over the adhesion layer 202, as shown in FIG. 2G, is interconnecting structure 130, in accordance with some embodiments.

FIGS. 3A-3H are cross-sectional views of a sequential process flow of forming a package 100, in accordance with some embodiments. In the embodiment of FIG. 3A, interconnecting structure 130 is formed on an adhesive layer 302, which is over a carrier 301. The formation process and the features of the interconnecting structure 130, in accordance with some embodiments, have been described above in FIGS. 2A-2G. Carrier 301 is similar to carrier 201 and adhesion layer 302 is similar to adhesion layer 202, in some embodiments. After the interconnecting structure 130 is formed, dies 120 are placed over interconnecting structure 130, as shown in FIG. 3B in accordance with some embodiments. As shown in the more detailed view of FIG. 1A, contacts 122 on dies 120 are placed directly over and come in contact with contacts 133 of interconnecting structure 130. In some embodiments, a reflow process is performed to bond contacts 122 to contacts 133. After contacts 122 and 133 are bonded together, an underfill (UF) is applied to fill the space between dies 120 and the surface of interconnecting structure 130, in some embodiments. FIG. 1B shows an underfill 144 filing the space between dies 120 and the surface of interconnecting structure 130. As mentioned above, the reflow and the application of underfill are not performed in some embodiments, as shown in FIG. 3B.

After dies 120 are placed on interconnecting structures 130, package structures 110 are placed on interconnecting structure 130, as shown in FIG. 3C in accordance with some embodiments. Connectors 119 on package structures 110 are placed directly over and come in contact with contacts 134 on interconnecting structure 130, as depicted in FIG. 1A. As mentioned above, contacts 134 are larger than contacts 133 because connectors 119 of package structure 110 are larger than contacts 122 on dies 120.

Afterwards, a reflow process is performed to bond contacts 134 with connector 119 and also to bond contacts 133 to contacts 122, as shown in FIG. 3D in accordance with some embodiments. The reflow process bonds both dies 120 and package structures 110 to interconnecting structure 130. As mentioned above, a reflow could have been performed after dies 120 are placed on interconnecting structure 130. Under such circumstance, the reflow, as depicted in FIG. 3D, only bonds contacts 134 to connectors 119.

After the reflow process is completed, molding layer 145 is applied to cover package structures 110 and dies 120, as shown in FIG. 3E in accordance with some embodiments. As mentioned above, molding layer 145 also acts as an underfill (UF) and fills the space between die 120 and interconnecting structure 130 in some embodiments. While, in some other embodiments, molding layer 145 also under-fill die 120.

In FIG. 3F, carrier 301 and adhesion layer 302 are removed, in accordance with some embodiments. As mentioned in FIG. 2C, a barrier layer 205 is formed to line openings 204. The barrier layer 205, for example a Ti layer, is removed to expose conductive layer 208, which is made of copper in accordance with some embodiments.

In FIG. 3G, connecting elements 140, such as solder balls, are mounted on a surface of interconnecting structure 130 to bond with contacts 135, in accordance with some embodiments. The bonding process also involves a reflow.

After the connecting elements 140 are bonded to the interconnecting structure 130, the package structure shown in FIG. 3G are secured to a tape, which is secured to a carrier (not shown). The carrier with the secured package structure of FIG. 3G then undergoes a sawing process to separate package 100 into individual packages. After the sawing process, the tape and carrier are separated from each package 100 (de-tape and de-bond from carrier). FIG. 3H shows a package 100 after the sawing and de-tape/de-bond processes.

The bonding structures formed between dies 120, package structure 110, connecting elements 140, and interconnecting structure 130 are merely some embodiments. Other types of bonding structures with different shapes and material layers are also possible.

The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

One aspect of this description is related to a method of forming a semiconductor package. The method includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

Another aspect of this description is related to a method of making a semiconductor package. The method includes forming an interconnecting structure, wherein the interconnecting structure includes a first redistribution layer (RDL) and a second RDL spaced from the first RDL, and the interconnecting structure has a thickness equal to or less than about 30 μm. The method further includes bonding a semiconductor die to the first RDL using a first bonding structure. The method further includes bonding the semiconductor die to the second RDL using a second bonding structure. The method further includes bonding a package structure to the first RDL using a third bonding structure. The method further includes bonding the package structure to the second RDL using a fourth bonding structure, wherein the semiconductor die is between the package structure and the interconnecting structure.

Still another aspect of this description relates to a method of making a semiconductor package. The method includes forming an interconnecting structure, wherein the interconnecting structure comprises a first redistribution layer (RDL). The method further includes bonding a first semiconductor die to the first RDL using a first bonding structure having a first width. The method further includes bonding a first package structure to the first RDL using a second bonding structure having a second width different from the first width, wherein the first package structure is on an opposite side of the first semiconductor die from the interconnecting structure, and an overall height of the semiconductor package ranges from about 350 microns (μm) to about 1050 μm.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. A semiconductor package comprising: a redistribution layer (RDL); a first semiconductor die disposed over the RDL, wherein the RDL has outermost sidewalls that extend laterally beyond outermost sidewalls of the first die, such that the RDL is wider than the first die and enables fan-out connection of the first semiconductor die; a die package disposed over the first semiconductor die and over the RDL, the die package bonded to the RDL by a plurality of conductive bump structures; and an encapsulant disposed over the RDL, wherein the encapsulant encloses the first semiconductor die and surrounds sidewalls of the plurality of conductive bump structures and surrounds the die package.
 2. The semiconductor package of claim 1, wherein the first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL includes a first conductive layer and a second conductive layer.
 3. The semiconductor package of claim 2, further comprising: a first contact connecting a contact pad of the plurality of contact pads of the first semiconductor die to the second conductive layer in the RDL.
 4. The semiconductor package of claim 3, further comprising: a second contact connecting a conductive bump structure of the plurality of conductive bump structures to the second conductive layer in the RDL; and wherein the first contact has a first width, and the second contact has a second width, the second width being greater than the first width.
 5. The semiconductor package of claim 1, wherein the die package comprises: a second semiconductor die; and a third semiconductor die.
 6. The semiconductor package of claim 5, wherein the encapsulant contacts an upper surface and sidewalls of the die package.
 7. The semiconductor package of claim 5, wherein the encapsulant contacts a top surface of the first semiconductor die and a bottom surface of the die package.
 8. The semiconductor package of claim 5, wherein the die package further comprises: one or more package contacts on a surface of the die package and being electrically coupled to the RDL; and one or more wires electrically coupling the one or more package contacts to the second semiconductor die and/or the third semiconductor die.
 9. The semiconductor package of claim 1, wherein an overall height of the die package ranges from about 350 microns to about 1050 microns.
 10. The semiconductor package of claim 1, wherein the RDL has a thickness equal to or less than about 30 microns.
 11. A semiconductor package comprising: a redistribution layer (RDL); a first semiconductor die disposed over the RDL, the first semiconductor die including a plurality of contact pads electrically coupled to the RDL, wherein the RDL enables fan-out connection of the first semiconductor die; and a die package disposed over the first semiconductor die and over the RDL, the die package coupled to a first surface of the RDL by a plurality of conductive bump structures, wherein the plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
 12. The semiconductor package of claim 11, further comprising: an encapsulant disposed over the RDL, wherein the encapsulant encloses the first semiconductor die and surrounds sidewalls of the plurality of conductive bump structures and surrounds the die package.
 13. The semiconductor package of claim 11, further comprising: a first contact connecting a contact pad of the plurality of contact pads of the first semiconductor die to the RDL.
 14. The semiconductor package of claim 13, further comprising: a second contact connecting a conductive bump structure of the plurality of conductive bump structures to the RDL; and wherein the first contact has a first width, and the second contact has a second width, the second width being greater than the first width.
 15. The semiconductor package of claim 11, wherein an overall height of the die package ranges from about 350 microns to about 1050 microns.
 16. The semiconductor package of claim 11, further comprising a molding layer covering the die package and the first semiconductor die.
 17. The semiconductor package of claim 16, wherein the molding layer contacts a top surface of the first semiconductor die and a bottom surface of the die package.
 18. A semiconductor package comprising: a redistribution layer (RDL) including a first metal layer and a second metal layer, the second metal layer stacked over the first metal layer and coupled to the first metal layer through a via; a first semiconductor die disposed over the RDL, the first semiconductor die including a plurality of contact pads electrically coupled to the RDL, wherein the RDL enables fan-out connection of the first semiconductor die; and a second semiconductor die disposed over the first semiconductor die and over the RDL, the second semiconductor die bonded to the RDL by a plurality of conductive bump structures, wherein the plurality of conductive bump structures have uppermost surfaces that are level with an uppermost surface of the first semiconductor die and wherein an overall height of the semiconductor package ranges from about 350 microns to about 1050 microns.
 19. The semiconductor package of claim 18, wherein the RDL has a thickness equal to or less than about 30 microns.
 20. The semiconductor package of claim 18, further comprising a molding layer encapsulating at least one of the first semiconductor die and the second semiconductor die. 